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    International Journal of Innovative Science and Research Technology
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    Important block of a central processing unit in any computing system is Arithmetic and Logic Unit (ALU). Among all the arithmetic operations, division is considered to be more complicated and it completes after several cycles of time. Latency is increased because of the clock cycles. It is frequently utilized in the areas of signal and image processing applications. This work describes the architecture of a serial divider in combination with the influence of Han Carlson adder. Adder along with the non-restoring algorithm has been tested for the design of divider in the DADENCE platform. And found 48.67% reduction in delay over the existing method.

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    Important block of a central processing unit in any computing system is Arithmetic and Logic Unit (ALU). Among all the arithmetic operations, division is considered to be more complicated and it completes after several cycles of time. Latency is increased because of the clock cycles. It is frequently utilized in the areas of signal and image processing applications. This work describes the architecture of a serial divider in combination with the influence of Han Carlson adder. Adder along with the non-restoring algorithm has been tested for the design of divider in the DADENCE platform. And found 48.67% reduction in delay over the existing method.

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    © All Rights Reserved
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    36 views3 pages

    Design of Efficient Serial Divider Using HAN CARLSON Adder

    Uploaded by

    International Journal of Innovative Science and Research Technology
    Important block of a central processing unit in any computing system is Arithmetic and Logic Unit (ALU). Among all the arithmetic operations, division is considered to be more complicated and it completes after several cycles of time. Latency is increased because of the clock cycles. It is frequently utilized in the areas of signal and image processing applications. This work describes the architecture of a serial divider in combination with the influence of Han Carlson adder. Adder along with the non-restoring algorithm has been tested for the design of divider in the DADENCE platform. And found 48.67% reduction in delay over the existing method.

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    © All Rights Reserved
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    of 3

    Volume 3, Issue 11, November – 2018 International Journal of Innovative Science and Research Technology

    ISSN No:-2456-2165

    Design of Efficient Serial Divider Using HAN


    CARLSON Adder
    Dr B. Senthilkumar, R. Gowrishankar
    Professor, Department of ECE
    KIT- Kalaignarkarunanidhi Institute of Technology
    Coimbatore, Tamilnadu, India – 641402

    Abstract:- Important block of a central processing unit iteration. Intel Pentium-4 Processor makes use of SRT
    in any computing system is Arithmetic and Logic Unit division [1] and [6]. Division operation consumes more time
    (ALU). Among all the arithmetic operations, division is when compared to addition, subtraction and multiplication
    considered to be more complicated and it completes [2] and [3]. Fast division method can be used but there is
    after several cycles of time. Latency is increased because complexity in the structure when compared to the slow
    of the clock cycles. It is frequently utilized in the areas of division. Thus an efficient algorithm which can improve the
    signal and image processing applications. This work efficiency should be followed.
    describes the architecture of a serial divider in
    combination with the influence of Han Carlson adder. II. TYPES OF EXISTING DIVISION
    Adder along with the non-restoring algorithm has been ALGORITHMS
    tested for the design of divider in the DADENCE
    platform. And found 48.67% reduction in delay over the Many algorithms used for serial division. Decimal
    existing method. division uses the traditional method which done normally i.e.
    the use of pencil and paper method [6]. The iterative process
    Keywords:- Cadence, Han Carlson Adder, Serial divider, of the subtraction and shifting operation is carried out for
    Non Restoring Algorithm, Delay. certain steps and hence called digit recurrence division
    algorithm [6]. In the digit recurrence algorithm, single
    iteration calculates one bit of the quotient. Partial remainder
    I. INTRODUCTION
    which is obtained by shifting is compared with multiples of
    the divisor for determining quotient bit. The control unit of
    Division operation is mainly used in scientific
    this recurrence algorithm contains the Adder/subtractor
    computation of image and digital signal processing. It can
    modules which makes implementation of the algorithm easy
    be accomplished either by serial division or parallel
    and high level of accuracy. There occurs cerain disadvantage
    division. Serial division is slow when compared to parallel
    like more timing complexity due to this algorithm, when
    division but its structure is very simple. Parallel division is
    compared with multiplicative division algorithm [4] and [6].
    fast when compared to the former one but its structure is very
    complex. Division algorithm falls into two main categories,
    There are three types of digit recurrence algorithm like
    slow division and fast division, slow division includes
    restoring, non- restoring and SRT [6]. For multiplicative
    restoring and non-restoring division, whereas fast division
    type of division algorithm, iteration is functional which uses
    methods include Newton Raphson and Goldschmidt method
    convergence techniques, starting from initial estimation till
    of division [7].
    the determination of quotient with required accuracy and
    SRT is used. This algorithm leads to high performance
    In conventional method of processing, digital division
    when compared to the existing recurrence division
    operation performs subtracting the divider from a reference
    algorithm. The demerits of this algorithm are that it has
    number, referred to as a current number which normally
    complex steps and it requires more number of computations
    requires that the divider be added back to the current
    required to get the final remainder. This type of division is
    number depends on the result of the subtraction stage. In
    possibly seen in commercial applications like
    non-restoring method the selection of either addition or
    microprocessors and mainframe computers [3] and [4].
    subtraction is carried out in the next computation stage [7].
    Another method which is also a functional iteration based
    Hence, the implementation of above requirement needs not only logic it
    algorithm is called Newton-Raphson method. Gold
    also needs large circuitry. Due to the above this a pretty good
    Schimdt’s algorithm is the another algorithm for functional
    amount of logic and related circuitry are required to
    iteration where both numerator and denominator are
    implement restoring and non-restoring division algorithms.
    multiplied with the same number and thus the fractional
    Digital recurrence is the simple and widely implemented
    class of division algorithm. The most common value remains same.
    implementation of digit recurrence division in modern
    microprocessors is division from the initials of Sweeney (S),
    Robertson (R) and Tocher (T) named SRT, who developed
    the algorithm independently at approximately the same time.
    SRT division uses subtraction as the fundamental operator
    in order to have a fixed number of quotient bits in each

    IJISRT18NV364 www.ijisrt.com 661


    Volume 3, Issue 11, November – 2018 International Journal of Innovative Science and Research Technology
    ISSN No:-2456-2165
    III. NON RESTORING SERIAL DIVISION
    ALGORITHM

    Digit recurrence algorithm is the most common


    algorithm though there were many literatures about several
    division algorithms. This algorithm is again divided into
    SRT type [6], restoring and non-restoring algorithm. The
    Digit is the basic algorithm in which a non-restoring
    algorithm is used to design a digital serial divider. Generally
    recurrence algorithm mentioned above makes use of
    iterative addition, subtraction and shifting operations in
    order to perform the division process. Division based on
    digital serial approach is simple and cheap whereas parallel
    digital division approach has high costly and increased
    complexity. Digital serial division is much slower when
    compared to parallel approach. But the design of hardware is
    complex and also parallel approach is expensive which
    serves to be a tradeoff while choosing either serial approach
    or digital parallel type of division [4].
    Fig 1:- Structure of Han Carlson Adder
    The digital serial division architecture based on the
    non-restoring type of division technique is used. For this The architecture of serial division is implemented
    particular digital design, the required remainder and using a 16-bit adder and subtractor unit. The adder and
    corresponding quotients in non-restoring type of division is subtractor unit are the first and important blocks of serial
    found by using the iterative process of add/subtract and shift divider. Its operation has been verified by giving suitable
    [4]. Here the adder cell used is Han Carlson adder. The inputs.
    adder cell is controlled by quotient determined in the
    previous step in order to perform the addition or subtraction. VI. EXPERIMENTAL RESULTS
    With the help of shift register, the partial remainder is shifted
    to get the required output. Comparison of existing serial divider module and
    proposed module in terms of delay is given in Table 1.
    IV. EXISTING SYSTEM

    Ripple carry adder (RCA) is used in the existing serial Delay of Existing System 55.28ns
    division technique. RCA is the simplest type of adder [2]. It
    Delay of Proposed System 26.904ns
    consists of series of full adder till ‘n’ bits. RCA architecture
    is simple to design and for more number of bits processing Table 1:- Comparison of Proposed System
    this simple structure may take some time period to process.
    The delay can be reduced if the structure of the RCA is
    modified in the existing adder. By keeping this into
    consideration the methods have been proposed for adders.
    One of the suitable addition methods for the divider is Han
    Carlson adder.

    V. IMPLEMENTATION OF PROPOSED SYSTEM

    Han Carlson adder along with non-restoring technique


    is used in the proposed design of serial divider. It also
    functions with the parallel prefix adder concept [1]. It has
    black cells, gray cells and buffer. Black cell is the
    combination of one OR gate and two AND gate. White cell
    is the combination of OR and AND gate. Buffer gives
    output value same as input value. Whereas it differs from
    other adder and it can be utilized for large word sizes. On
    comparing with other adders Han Carlson has low latency
    [5]. VerilogHDL coding for the above logic has been done
    and has also been tested by using CADENCE platform. The Fig 2:- Result of Han Carlson Adder
    structure of Han Carlson adder is shown in fig.1.

    IJISRT18NV364 www.ijisrt.com 662


    Volume 3, Issue 11, November – 2018 International Journal of Innovative Science and Research Technology
    ISSN No:-2456-2165
    Communication Engineering (IJARECE), Volume 5,
    Issue 2, pp. 226-230, February 2016.
    [6]. R. Mishra, ‘An efficient VLSI architecture for a serial
    divider’, Devices for Integrated Circuit (DevIC),
    Kalyani, pp. 482-486, 2017.
    [7]. Suyash Toro, Y.V. Avinash Patil, S.C. Chavan, D.S.
    Bormane and Sushma Wadar, “Division operation
    based on Vedic Mathematics”, IEEE International
    Conference on Advances in Electronics,
    Communication and Computer Technology
    (ICAECCT), pp. 450-454, 2016.

    Fig.3: Result of Proposed Divider

    The simulated results have been given in Fig.2 and Fig


    .3 for Han-Carlson and the Proposed Divider respectively.

    VII. CONCLUSIONS

    Arithmetic divider is the primary block of image and


    signal processing applications. The proposed divider system
    featured with Han Carlson adder and Non- Restoring
    algorithm has been tested for many examples and found
    satisfactory results with the delay reduction of 26.904 ns
    which is 48.67% improvement in delay efficiency of the
    proposed system over the existing system. Results have
    been tested by using CADENCE platform.

    REFERENCES

    [1]. K.Swapna Gedam and P.Pravin Zode, “Parallel prefix


    Han Carlson Adder”, International Journal of Research
    in Engineering and Applied Sciences, Vol. 02, Issue 02,
    July 2014.
    [2]. Jasbir Kaur and Lalit Sood, “Comparison Between
    Various Types of Adder Topologies” IJCST Vol. 6,
    Issue 1, pp. 62–66, March 2015.
    [3]. A.S. Prabhu, B. Naveena, K. Parimaladevi, M.
    Samundeswari and P. Thilagavathy “Serial Divider
    Using Modified GDI Technique”, International Journal
    of Innovative Research in Electrical, Electronics,
    Instrumentation and Control Engineering, Vol. 3, Issue
    10, pp. 73-76, October 2015.
    [4]. Jen-Shiun Chiang, Hung-Da Chung and Min-Show
    Tsai,“Carry-Free Radix-2 Subtractive Division
    Algorithm and Implementation of the Divider”,
    Tamkang Journal ofScience and Engineering, Vol. 3,
    No. 4, pp. 249-255, 2000.
    [5]. K.Subha Jeyamala and B.S.Aswathy, “Performance
    Enhancement of Han – Carlson Adder”, International
    Journal of Advanced Research in Electronics and

    IJISRT18NV364 www.ijisrt.com 663

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