Verification “Hackathon” - Verilog/SystemVerilog/UVM
Are you a die-hard Verification fan? Are you looking to improve on your UVM skills in a real “bug hunting” event?  VerifLabs, www.veriflabs.com, a new venture from CVC (www.cvcblr.com) is pleased to announce a new session of our popular "Verification Hackathon” - use Verilog/SystemVerilog/UVM.

 As part of the Go2UVM initiative we are making every attempt to assist real engineers do real work to get going with the industry’s most popular, advanced Functional Verification framework – UVM.  

When: 23-Jan-2015, Friday,10.00 AM onwards (till evening) @ CVC, Bengaluru  Address: http://cvcblr.com/?page_id=2 

Cost:  FREE* if no feedback/analysis is requested.
          Rs. 500 /-- if you need feedback and analysis on how you performed (Analysis, detailed code review will be provided by our experts team)

All Attendees will have the option of buying the best selling SVA book at 10% discount, see: http://verifnews.org/publications/books/   

Hurry, limited seating, first-come-first-serve basis

Agenda:
• Introduction
• Problem statement (Specification along with RTL)
• Code-it, “hack-it” - find those “Design errors/bugs” lurking around the “Encrypted RTL”
• Feedback, analysis for paid contestants

Schedule:  
• Date: 23-Jan-2015, Friday
• Time: 10.00 AM to 5.00 PM
• Venue: CVC, Bengaluru
• Address: http://cvcblr.com/?page_id=2 
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Are you looking for feedback on your performance at the event (Cost Rs. 500/- ) *
Our basic Hackathon is free of cost, provides a platform to test your skills, readiness for next job etc. However if you need our engineering efforts to analyze your performance and provide you feedback, then we charge a small amount
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